The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
Semiconductor devices are fabricated by creating a sequence of patterned and un-patterned layers where the features on patterned layers are spatially related to one another. Thus during fabrication, each patterned layer aligns to a previous patterned layer, and as such, an overlay between a first layer and a second layer is taken into account. The overlay is the relative position between two or more layers of a semiconductor substrate such as, for example, a wafer. As semiconductor processes evolve to provide for smaller critical dimensions, and devices reduce in size and increase in complexity including number of layers, the alignment precision between layers becomes increasingly more important to the quality, reliability, and yield of the devices. The alignment precision is usually measured as overlay offset or overlay error, or the distance and direction which a layer is offset from precise alignment with a previous layer. Misalignments can result in reduced device performance or complete device failure. Conventional overlay metrology is used to check alignment but has not been satisfactory in all regards. It is desired to have improvements in this area.